phase-locked loop

An Thyristor Medium-frequency Power Supply Startup Circuit Based on Phase-locked Loop

基于锁相环技术的晶闸管中频电源启动电路

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5Gb/ s CMOS Monolithic Clock Recovery Circuit Rased on Half-rate Phase-locked Loop

基于半速率锁相环的5Gb/s CMOS单片时钟恢复电路

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the paper studies digital control scheme of resonance inverter frequency-tracking based on all digital phase-locked loop.

本文主要研究了基于全数字锁相环的谐振型逆变器频率跟踪的数字化控制方案.

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Behavior Modeling of PLL and Its Application in Video Horizontal PLL Optimized implementation scheme of three phase phase-locked loop based on FPGA

锁相环行为级建模及在视频行锁相中的应用基于FPGA的三相锁相环的优化设计方案

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article concludes with a phase-locked loop phase noise improvement approach.

文中最后提出了改善锁相环相位噪声的办法.

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The source consists of a microwave phase-locked loop and a new type of automatic frequency control circuit. Chief factors to influence spectrum purity of microwave output signal and phase noise are analyzed.

该稳定本振源由一个微波锁相环路（PLL）和一种新型自动频率控制电路（AFC）组成，文中分析了影响微波输出信号频谱纯度和相位噪声的主要因素。

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Ameliorating to Track the Series Resonant Frequency of the Ultrasonic Vibration System with Phase-Locked Loop

锁相环跟踪超声振动系统谐振频率的改进

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Design of Charge Pump for High-Speed Phase-Locked Loop

高速PLL电路中的电荷泵电路设计

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and the working principle of the phase-locked loop.

然后阐述锁相环的工作原理.

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this paper focused on the modelling and parameter design of a period-controlled fully digital phase-locked loop.

研究了一种基于周期控制的逆变器全数字锁相环的建模和参数设计.

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Chaotic Phenomena of the Sampled Phase-Locked Loop System

采样锁相环系统的混沌现象

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Application of CSL Structure in Intergrated Phase-Locked Loop

CSL结构在集成锁相环中的应用

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The Application of Phase-Locked Loop To Frequency Changing Speed Regulation System for Synthetic Fibre Spinning Machine

锁相环路在化纤纺丝机变频调速系统中的应用

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The new method simplifies the detection circuit as well as improves response speed of the detection algorithm for it does not require phase-locked loop circuit.

该方法不需要锁相环电路，简化了检测电路结构，且提高了检测算法的响应速度。

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Normally, a phase-locked loop has a very narrow loop bandwidth for good jitter attenuation.

用于光纤传输系统的CRC必须满足抖动要求。如果用简单的锁相环（PLL）来满足这一要求的话，将意味着非常窄的环路带宽和非常小的锁定范围。

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The acquired three-phase voltage signals are used for software phase-locked loop. The phase information combined with the collected current signals to calculate of harmonic and reactive currents.

采集的三相电压信号，用于软件锁相，得到的相位信息结合采集到的三相电流信号共同完成谐波和无功电流的计算。

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we adopted phase-locked loop in order to assure synchronous sampling and accuracy of fft.

系统采用了硬件锁相环技术,来跟踪电网频率的变化,保证采样的同步和傅立叶变换的准确度.

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Realization Method of Software Clock Phase-locked Loop in Radio Remote Unit

射频拉远模块中软件时钟锁相的实现方法

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in the premise analyzing the principle of the driver circuits, the system developed uses the monolithic integrated phase-locked loop ( pll) and the double balance amplitude modulator, the isolated components are placed, so the difficulty of the rf signal transmission is resolved.

分析驱动器的工作原理，我们采用集成锁相环和双平衡幅度调制器，解决了分立元件高频电路设计复杂的困难；

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The phase-locked loop band-pass filter and the logarithmic amplifier is adopted in the circuit to insure the reliability of receiving signal.

电路中采用锁相带通滤波器和对数放大器，保证有效信号的可靠接收。

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Application of Integrated Circuit Phase-locked Loop in Measuring Pulse Duty Factor

IC锁相环在脉冲占空比测量中的应用

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Time difference counting method and phase-locked loop technology are adopted. A systematic phase-detection function module is designed. High-precision measurement of the phase difference is achieved. 4.

采用时间差计数法和锁相环技术，设计了系统的鉴相功能模块，实现了相位差的高精度测量。

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Finally, the impedance characteristic of piezoelectricity transducer and the principle of frequency tracking were studied. Software phase-locked loop was used to track self-adapting frequency, and arithmetic of frequency tracking based on change step and dichotomy was presented.

最后，对压电换能器的电抗特性和频率跟踪原理进行研究，采用软件锁相环进行了频率自适应跟踪设计，提出变步进与二分法相结合的频率跟踪算法。

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The Study of Simulation for Tracing Satellite Doppler Shift Using Third-order Phase-locked loop

三阶锁相环跟踪卫星多普勒频偏的仿真研究

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Realizing High Accurate Measurement by Simulation of the Equivalent Noise Bandwidth of Interferometer Phase-locked Loop

干涉仪锁相环等效噪声带宽高精度测量的仿真实现

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in phase-coherent communication system, phase-locked loop is always used to yield coherent reference signal.

相位相干通信系统中，通常采用锁相环路来产生相干参考信号。

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optimization of the phase-locked loop oscillator design of tdma receiver

TDMA接收机锁相本振源设计优化

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This paper introduced a system to pick up the bit alignment signal of digital phase-locked loop which is programmed in AHDL language and its CPU is CPLD ( Complicated Programmable Logic Device).

现介绍一种用CPLD复杂可编程逻辑器件为控制核心，采用AHDL语言编程实现数字锁相位同步信号提取的方法。

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a multi-layer charge-pump phase-locked loop behavioral model

一种电荷泵锁相环的多层行为级模型

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Validation through prototype testing, test results showed that the three-phase locked loop has achieved the synchronization requirements of the PV inverter system and gained a unit power factor for the inverter. Finally, this article used Verilog language to complete the design of FPGA-based three phase-locked loop.

通过样机试验验证，试验结果表明，本文所设计的三相锁相环达到了光伏逆变系统的同步性能要求，实现了逆变器的单位功率因数运行。

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